Verilog

linguagem de programação

Verilog HDLIEEE 1364

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essenceia.github.io·há 27 dias

Designing an Ethernet Switch ASIC

Designing the world's first open source Ethernet switch ASIC. An unmanaged cut-through 3-port 100Mbps switch fabbed on Global Foundries 180 nm.

essenceia.github.io·há cerca de 2 meses

Until Heat Death Do Us Part

Broadcasting over Ethernet until the heat death of the universe with a custom ASIC, or yet another terrible idea, this time inspired by reddit.

essenceia.github.io·há 5 meses

Floating point from scratch: Hard Mode

I have a confession to make: floating point scares me. Half a decade ago I decided that I was going to implement some floating point arithmetic. Back then it seemed approachable enough, after all, fl

essenceia.github.io·há 8 meses

Two weeks until tapeout

Chronicles of a bad idea. Or how I designed a systolic array with in-silicon debug infrastructure from scratch in under two weeks, and taped it out on Global Foundry 180 nm though a Tiny Tapeout exper

essenceia.github.io·há 8 meses

BLAKE2s Hashing Accelerator: A Solo Tapeout Journey

BLAKE2s ASIC implementation targetting the SKY130A process, tapedout with Tiny Tapeout.

essenceia.github.io·há quase 3 anos

MoldUDP64 and ITCH testbench

Top level testbench for the ITCH and MoldUPD64 modules.

essenceia.github.io·há quase 3 anos

ITCH RTL implementation

ITCH is a message protocol used in the application layer of financial exchanges that implement the ITCH/OUCH feeds. It is part of the exchange’s direct data feed, a low latency feed between the excha

essenceia.github.io·há quase 3 anos

Ethernet 10GBASE-R and 40GBASE-R PCS

RTL implementation of the Ethernet Physical Coding Sublayer (PCS) for 10Gb and 40Gb fiber optics.

Related Entities

1Systolic_Array27×
2Arithmetic27×
3130Nm27×
4Bfloat1624×
5Verification24×
6Float24×
7Math24×
8Floating Point24×
9Asic12×
10Rtl10×

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